DESIGN OF A MESSAGE PASSING RTOS FOR MULTI-CORE EMBEDDED SYSTEMS
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	eric.verhulst@lancelot.be

	docs : www.eonic.com

- Some history :
	- CSP, occam, transputers
	- CSP : Communicating Sequential Processes (Hoare)

- Virtuoso
  	- concepts : a pragmatic CSP with RTOS objects
	- distributed semantics ( > API )
  	- prioritized packet switching + comm protocol
	- low latency (comm), fully distributed, small (5 - 40 K)
	- mostly applied in parallel DSP (high throughput)

- Why needed ?
 	- power limits faster CPUs 	
	- complexity requires multi-cores : SoC platform based design
  	- heterogenous : open-source for economy of scale (porting !)
  	- PURE message passing
		- bus is bottleneck
		- "switch fabrics"
		- basis for fault-tolerance

- Design goals :
	- fully distrubited, hard real-time
	- very portable (drivers !)
	- scalable but reliable (>< side-effects)	
	- topology independent
	- static, pseudo-dynamic, [dynamic] : cfr. OSE

- proposal 
  	- based on Open Source : GPL + except. 
  	- steps to take
		- start with eCOS
		- design document
		- check eCOS API semantics 
		- implement prototype